The PIB Headquarters, on January 06, 2026, issued the Design Linked Incentive Scheme.
The following has been stated namely: -
• C-DAC has established the ChipIN Centre under the DLI Scheme to facilitate the design infrastructure support to approved companies::
• National EDA (Electronic Design Automation) Tool Grid: Remote access to the centralised facility of advanced EDA tools for chip design activities will be provided to start-ups and MSMEs.
• IP Core repository: Flexible access to the repository of IP Cores for SoC design activities.
• MPW Prototyping support: Fiscal support for fabricating the design in an MPW manner at semiconductor foundries.
• Post-silicon validation support: Fiscal support for testing and validation of the fabricated ASIC and silicon bring-up activities.
• The Design Linked Incentive (DLI) Scheme is critical to anchoring India in the most strategic and value-intensive segment of the global semiconductor value chain—chip design. By reducing dependence on imported semiconductor IPs and chips, strengthening resilience against geopolitical and supply-chain disruptions, and ensuring assured access to critical technologies for defence, telecom, AI and mobility, DLI lays the foundation for strategic autonomy and long-term economic growth. The scheme also enables high-value growth by translating deep-tech innovation into globally competitive products, fostering startups and MSMEs, and building a highly skilled engineering workforce.
[Press release no. 2211220]
